By K. Laudel, Applied Signal Technology, Inc
The viability of high order (64,256) QAM transmission techniques in a cable environment have recently been technically proven in extensive testing [1,2,3]. However, the economic goals of cable TV set-top terminal solutions for the demodulation of 64- and 256-QAM remain as the engineering challenge for modem designers. Current pricing for QAM demodulator chips will require a fairly significant reduction in cost within the next year to meet consumer demands as well as the competitive demands from market forces such as Direct Broadcast Satellite. One expedient method for cost reduction exists in the demodulation algorithms. Within the demodulator architecture, it is not uncommon for the adaptive equalizer to occupy upwards of 40-50 percent of the silicon area. Traditional, T-spaced and T/2- spaced equalizers have been the cornerstone of many of the currently proposed architectures [1,4]. However, there exists a strong economic motivation in the consumer marketplace for examining alternative equalizer structures in order to decrease the silicon area. The intent of this paper is to address the technical performance capabilities of an alternative equalizer architecture that could potentially result in an equalizer die area savings of approximately 33 percent. More specifically, laboratory and .field test results of a T/2-spaced prototype will be discussed and compared to simulation results of the proposed design.